The invention relates to the field of electronics, and, more particularly, to an integrated circuit including a resistor between two metal levels therein, as applied to a memory cell of a static random access memory.
A memory cell of a static random access memory typically includes four transistors and two resistors. The four transistors are formed in a semiconductor substrate and are mutually interconnected by a local interconnect layer. However, it is difficult to form the two resistors so that each memory cell is dense. The more dense a memory cell the less space required to form the static random access memory, which is particularly important if the memory incorporates a very large number of memory cells. Consequently, there is a continuing need to form a dense memory cell in a static random access memory.
An object of the invention is to use the space available between the vertical connections already existing between two metal levels for inserting a resistor there between.
Another object of the invention is to produce high-value resistors in a particularly straightforward manner.
Yet another object of the invention is to produce a particularly dense memory location in static random access memories.
First, a process according to the present invention produces an integrated circuit comprising a resistor placed between two metal levels of the integrated circuit. According to this process, an intermediate metal level is produced on the lower metal level. An electrically conductive layer on the lower face of a first part of the intermediate metal level rests on top of a portion of a metal track of the lower metal level via a thin layer of a dielectric material to form at least a first part of the resistor. The conductive layer is surrounded laterally by an intermediate insulating layer. An upper insulating layer supporting the upper metal level is deposited on the intermediate metal level, and a metal connection or via connects the second part of the conductive layer to a track of the upper metal level.
The dielectric layer portion sandwiched between the lower face of the first part of the electrically conductive layer and the portion of the metal track of the lower metal level forms the dielectric of a capacitor. The two electrodes of the capacitor are formed from the first part of the conductive layer and the metal track portion, respectively. However, the small thickness of this dielectric layer as compared with the thickness of the conductive layer and with that of the metal portion results in the formation of a low-value capacitor. This low-value capacitor leaks its charge when a potential difference is applied to its terminals, and therefore operates as a high-value resistor.
In a first embodiment of the invention, the first and second parts of the electrically conductive layer are identical. Also, the metal connection is produced by etching the upper insulating layer, and stopping on the upper face of the second part of the conductive layer. In other words, this embodiment allows compact vertical resistors to be produced.
Another embodiment includes shifting the second part of the conductive layer with respect to the first part. Starting with this, a first possibility is to produce the metal connection by etching the upper insulating layer, and stopping on the upper face of the second part of the conductive layer. Such an embodiment allows the upper metal level to be connected when it is not possible to produce a vertical resistor.
Another possibility is for the lower face of the second part of the conductive layer to be in contact with the dielectric layer above a portion of another metal track of the lower level. This forms a second part of the resistor electrically connected to the first part via the rest of the conductive layer. Thus, two resistors in series are formed. If required, the connection to the upper metal level is made by a metal connection in contact with another portion of this other metal track of the lower level.
Although the intermediate metal level can be produced in various ways, it is particularly advantageous to produce this metal level using a xe2x80x9cdamascenexe2x80x9d process, which is well known to those skilled in the art. In other words, production of the intermediate metal level comprises deposition of the intermediate insulating layer, etching of this insulating layer to define a cavity at the place where the conductive layer is, and then depositing the dielectric layer on the walls and the bottom of the cavity. The cavity is filled with an electrically conductive material to form the conductive layer.
When the lower metal level is a metal level 0, also called a local interconnect layer by those skilled in the art, the invention is particularly applicable to the production of memory locations having four transistors and two resistors forming a static random access memory.
More specifically, the invention also provides such an integrated static random access memory device having four transistors and two resistors. The four transistors are produced in a semiconductor substrate and are mutually interconnected by a local interconnect layer which lies under a first metal level (metal 1) and which forms, above the substrate, a base metal level (metal 0). The two resistors therefore extend in contact with a part of the local interconnect layer between the base metal level (metal 0) and the first metal level (metal 1). This makes it possible to obtain dense memory locations, thereby significantly minimizing the area of a static random access memory incorporating a very large number of these memory locations.
Several possibilities are presented for forming each of the resistors of this memory location. Each resistor may be formed from a layer of a resistive material resting at its two ends on two portions of the local interconnect layer. It is also possible for each resistor to be formed from a layer of an electrically conductive material. This material rests at its two ends on two portions of the local interconnect layer. A resistor is formed from two thin layers of a dielectric material placed respectively at the two ends of the electrically conductive layer between this electrically conductive layer and the corresponding portion of the local interconnect layer.
Regardless of the embodiments used, even in combination, each resistor contacts on a first local interconnect layer portion for producing the interconnect between the gate of one memory transistor and the drain of the other memory transistor, and contacts on a second local interconnect layer portion connected to the first metal level by a metal interconnect via. The shape of each resistor therefore partially matches a shape of the gate of the memory transistor.